Flip-flops are key elements in contemporary high-speed integrated circuit design. High clock frequencies are generally gained by using a fine-grained pipeline having minimal logic levels inserted between pipeline stages. Power dissipated by the clock and flip-flops constitute a substantial portion of a total power budget due to the high number of pipeline stages. Therefore, the design of high-performance flip-flops with reduced power dissipation is a major concern in modern high-performance applications. At the same time, die size is a limiting factor that should not be sacrificed for speed or power. In addition, circuit stability and race margin are yet another issues affecting flip-flop selection for high-performance integrated circuits.
A PowerPC Master-Slave Latch (MSL) is one of the fastest classical flip-flop structures known in the art due to a short direct path and a low-power feedback path. The MSL exhibits many favorable characteristics including a small transistor count, which makes it a favorite among skilled artisans. The MSL is also found in many standard cell libraries. However, the MSL has a large clock load, which increases power consumption.
Another known structure is a sense amplifier based flip-flop 10, which is depicted in FIG. 1, also exhibits a small transistor count and therefore a small die size. The sense amplifier based flip-flop 10 has a clock load that is less than the clock load of the MSL and therefore exhibits reduced power consumption.
The sense amplifier based flip-flop 10 includes a sense amplifier stage 12 and a set-reset latch stage 14. The sense amplifier stage 12 is operative to receive a clock signal 16 and complementary input signals 18 and 20. The sense amplifier stage 12 generates a set signal 22 and a reset signal 24 based on the clock signal 16 and the complementary input signals 18, 20. More specifically, when the clock signal 16 is low, nodes 26 and 28 are pre-charged to Vdd and transistors 30 and 32 are on holding their source terminals at “Vdd-Vtn”. In this phase, the latch stage 14 holds an output signal 34 at a constant state. At a rising edge of the clock signal 16, the sense amplifier stage 12 senses the complementary input signals 18 and 20 and one of the pre-charged nodes 26 or 28 is pulled down a low level thorough transistor 30 or 32, while the other pre-charged node 26 or 28 remains at Vdd. The latch stage 14 receives signals 22 and 24 and stores new data, which is represented by the complementary signals 18 and 20. When the sense amplifier stage 12 switches, one of transistors 30 or 32 changes a state of nodes 22 or 24 first. After, one of transistors 30 or 32 transition both source terminals are held at ground. Therefore, any subsequent transition of the complementary input signals 18, 20 cannot modify the set and reset signals 22, 24. In addition, transistor 36 is driven by Vdd, which provides for a static operation. More specifically, since transistor 36 is always on, a pull-down path for either node 26 or 28 exists even if the complementary input signals 18, 20 transition while the clock signal 16 is at the high level.
Although this circuit exhibits desirable characteristics, it also suffers from an imbalanced delay, which increases power consumption. More specifically, when the clock signal 16 transitions to a high or low level, the set or reset signal 22, 24 may also transition. The configuration of the sense amplifier stage 12 ensures that the set signal 22 transitions in the same amount of time as the reset signal 24. However, the configuration of the latch stage 14 creates an imbalanced delay. More specifically, when the set signal 22 transitions, a transition of the output signal 34 is delayed by a first delay due to NAND gate 38. When the reset signal 24 transitions, a transition of the output signal 34 is delayed by a second delay that is greater than the first delay due to NAND gates 38 and 40.
In one method, the latch stage 14 is modified to minimize the imbalanced delay. However, modifying the latch stage 14 to minimize the imbalanced delay requires an increased number of transistors, which increases the area of the sense amplifier based flip-flop 10.
It is therefore desirable, among other things, to provide an improved sense amplifier based flip-flop.